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<div class="header">
  <div class="headertitle"><div class="title">DBGMCU_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>Debug MCU.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:a0cc3561c124d06bb57dfa855e43ed99f" id="r_a0cc3561c124d06bb57dfa855e43ed99f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0cc3561c124d06bb57dfa855e43ed99f">IDCODE</a></td></tr>
<tr class="memitem:a15981828f2b915d38570cf6684e99a53" id="r_a15981828f2b915d38570cf6684e99a53"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a15981828f2b915d38570cf6684e99a53">CR</a></td></tr>
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</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Debug MCU. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="aec754f328723263fec5e157d06720128" name="aec754f328723263fec5e157d06720128"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aec754f328723263fec5e157d06720128">&#9670;&#160;</a></span>APB1HFZ1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::APB1HFZ1</td>
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</div><div class="memdoc">
<p>Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 </p>

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<a id="ade78d6c1b3af2409a6b3a7f7ccc62db3" name="ade78d6c1b3af2409a6b3a7f7ccc62db3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ade78d6c1b3af2409a6b3a7f7ccc62db3">&#9670;&#160;</a></span>APB1LFZ1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::APB1LFZ1</td>
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</div><div class="memdoc">
<p>Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C </p>

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<a id="a1da46d5c89c571f80d2976cd3cabaa52" name="a1da46d5c89c571f80d2976cd3cabaa52"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1da46d5c89c571f80d2976cd3cabaa52">&#9670;&#160;</a></span>APB2FZ1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::APB2FZ1</td>
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</div><div class="memdoc">
<p>Debug MCU APB2FZ1 freeze register, Address offset: 0x4C </p>

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<a id="a49a2f06534a2aa7c963e33fb819ed717" name="a49a2f06534a2aa7c963e33fb819ed717"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a49a2f06534a2aa7c963e33fb819ed717">&#9670;&#160;</a></span>APB3FZ1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::APB3FZ1</td>
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      </table>
</div><div class="memdoc">
<p>Debug MCU APB3FZ1 freeze register, Address offset: 0x34 </p>

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<a id="a11a649a39dcd7c14e9d08c02fdf23188" name="a11a649a39dcd7c14e9d08c02fdf23188"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a11a649a39dcd7c14e9d08c02fdf23188">&#9670;&#160;</a></span>APB4FZ1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::APB4FZ1</td>
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<p>Debug MCU APB4FZ1 freeze register, Address offset: 0x54 </p>

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<a id="a4251fb34556fa52aaded20acdfa3c09e" name="a4251fb34556fa52aaded20acdfa3c09e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4251fb34556fa52aaded20acdfa3c09e">&#9670;&#160;</a></span>CIDR0</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::CIDR0</td>
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</div><div class="memdoc">
<p>Debug MCU component identity register 0, Address offset: 0xFF0 </p>

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<a id="a929f2d4e6fa1f7d8acf7a85f60d729aa" name="a929f2d4e6fa1f7d8acf7a85f60d729aa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a929f2d4e6fa1f7d8acf7a85f60d729aa">&#9670;&#160;</a></span>CIDR1</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::CIDR1</td>
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<p>Debug MCU component identity register 1, Address offset: 0xFF4 </p>

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<a id="a899def83ae7e50fd889b0ff3a7200b87" name="a899def83ae7e50fd889b0ff3a7200b87"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a899def83ae7e50fd889b0ff3a7200b87">&#9670;&#160;</a></span>CIDR2</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::CIDR2</td>
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<p>Debug MCU component identity register 2, Address offset: 0xFF8 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa0c05391c70942f7b6d70d9a7669fff1">&#9670;&#160;</a></span>CIDR3</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::CIDR3</td>
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<p>Debug MCU component identity register 3, Address offset: 0xFFC </p>

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<a id="a15981828f2b915d38570cf6684e99a53" name="a15981828f2b915d38570cf6684e99a53"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a15981828f2b915d38570cf6684e99a53">&#9670;&#160;</a></span>CR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::CR</td>
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<p>Debug MCU configuration register, Address offset: 0x04 </p>

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<p>MCU device ID code, Address offset: 0x00 </p>

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<p>Debug MCU peripheral identity register 0, Address offset: 0xFE0 </p>

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<p>Debug MCU peripheral identity register 1, Address offset: 0xFE4 </p>

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<p>Debug MCU peripheral identity register 2, Address offset: 0xFE8 </p>

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<p>Debug MCU peripheral identity register 3, Address offset: 0xFEC </p>

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<p>Debug MCU peripheral identity register 4, Address offset: 0xFD0 </p>

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<p>Reserved, Address offset: 0xFD4-0xFDC </p>

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<p>Reserved, Address offset: 0x08 </p>

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<p>Reserved, Address offset: 0x38 </p>

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<p>Reserved, Address offset: 0x40 </p>

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<p>Reserved, Address offset: 0x48 </p>

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<p>Reserved, Address offset: 0x50 </p>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DBGMCU_TypeDef::RESERVED9[990]</td>
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<p>Reserved, Address offset: 0x58-0xFCC </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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